Conventionally, as a vertical switching element for an inverter or the like, for example, a semiconductor device having a reverse-conducting IGBT (RC-IGBT) structure that includes the IGBT and the FWD in one chip has been known.
In such a semiconductor device, a base layer is arranged at a surface layer portion of a semiconductor substrate including an N−-type drift layer and a trench gate structure is arranged to penetrate the base layer.
A P-type collector layer and an N-type cathode layer are arranged adjacent to a rear surface of the semiconductor substrate. An N-type emitter region is arranged at a portion of the base layer located above the collector layer. An upper electrode electrically connected to the base layer and the emitter region is arranged on a front surface of the semiconductor substrate. A lower electrode electrically connected to the collector layer and the cathode layer is arranged on the rear surface of the semiconductor substrate. That is, a region in which the collector layer is arranged at the rear surface of the semiconductor substrate is defined as an IGBT region, and a region in which the cathode layer is arranged at the rear surface of the semiconductor substrate is defined as a diode region. In other words, in the above semiconductor device, a boundary between the collector layer and the cathode layer corresponds to a boundary between the IGBT region and the diode region.
In the semiconductor device including the IGBT region and the FWD region in one chip, the P-type collector layer has relatively low concentration considering a switching loss of the IGBT. In a recovery operation of the FWD, holes are not sufficiently implanted from the low-concentration collector layer in the IGBT region and a recovery waveform vibrates. That is, in the recovery operation of the FWD, carriers are depleted at the rear surface of the semiconductor substrate and a vibration of an anode-cathode voltage is caused by a parasitic capacitor and a parasitic inductor of an external circuit. Due to the vibration, a surge voltage is likely to increase.
In order to further decrease on-resistance, a thickness of the semiconductor device, specifically, a thickness of the drift layer is reduced. However, when the thickness of the semiconductor substrate is reduced, withstand voltage of the semiconductor device decreases because the depletion layer is likely to reach the rear surface of the semiconductor substrate in the switching off of the IGBT. Also, when the thickness of the semiconductor substrate is reduced, holes are depleted and vibration of collector voltage waveform is likely to occur in the switching.
On the other hand, when an impurity concentration of the collector layer is increased, the amount of the implanted holes increases. As a result, the vibrations of the recovery waveform and the collector voltage waveform and the increase of the surge voltage are restricted. However, the switching loss of the IGBT increases. Accordingly, reduction of the surge voltage and reduction of the switching loss of the IGBT are in a trade-off relationship and there is a difficulty in achieving both. Especially, recent minute cell structure having narrow trench gate intervals stores more holes and the holes are likely to remain in the semiconductor substrate. In such a minute cell structure, the impurity concentration of the collector layer at the rear surface of the semiconductor substrate needs to be decreased not to increase the switching loss. As a result, the vibration of the recovery waveform of the FWD is more notable.
To address the above situations, it has been known to arrange an N-type layer having high impurity concentration in the drift layer of the cell region of the semiconductor device in which the IGBT is arranged (for example, see JP 5320679 B2).
Also, it has been known to arrange an N-type layer in a reverse-blocking IGBT (RB-IGBT) to improve reverse withstand voltage. Specifically, in the cell region in which the IGBT and the FWD is arranged, the N-type layer is arranged adjacent to a surface of the drift layer at which the trench gate structure is arranged, that is, the N-type layer is arranged adjacent to a front surface of the drift layer. When the thickness of the drift layer is 100 micrometer (μm), the N-type layer is arranged at a position having a depth of 10 μm from the front surface of the drift layer. That is, the N-type layer is arranged at the position having a depth of 10% of the thickness of the drift layer. As such, the reverse withstand voltage is improved.